TL;DR

If you want to deploy some logic to a FPGA and talk to that logic over PCIE, and you want to stream data to that logic, it’s surprisingly confusing how to wire everything together. It can be done using Xilinx’s DMA/Bridge Subsystem for PCI Express. Here’s what it looks like when it’s all done:

One thing that made figuring this out challenging is that while there’s an abundance of guides that employ the Zynq platform (including the adjacent ARM core functioning as the processor system), there are almost none for that discuss accomplishing the goal using other boards/chips/configurations.

Disclaimer

Since so much of the tooling around FPGAs is proprietary (and thus brittle as hell) it’s worth mentioning that I got this to work using 2021.1 Xilinx tools and on an Artix 7 (PicoEVB with XC7A50T-CSG325-1). YMMV (in particular, with regards to the ports).

Acronyms

• FPGA: Field Programmable Gate Array; the device which we’re programming.
• CPU: Central Processing Unit; the processor on the host device.
• I/O: Input/Output; self-explanatory.
• PCIE: Peripheral Component Interconnect (Express); the communication interface we’re using to communicate with the host device (i.e., the CPU and operating system and memory).
• AXI: Advanced eXtensible Interface; the communication interface that the components will use to communicate amongst themselves, on the FPGA itself.
• DMA: Direct Memory Access; a system that lets individual components access memory directly, independently of the CPU.
• MMIO: Memory-Mapped I/O; uses the same address space to address both memory and I/O devices. The memory and registers of the I/O devices are mapped to (associated with) address values (in the address range assigned by the DMA controller).
• IP: Intellectual Property; wacky name for a module/chunk of logic.
• RTL: Register-Transfer Level; circuits designed in terms signals and registers.
• HLS: High-Level Synthesis; a technique for translating procedural code (e.g., C++) to RTL designs.
• SPI: Serial Peripheral Interface; a synchronous serial communication interface specification used for short-distance communication, primarily in embedded systems.
• JTAG: Joint Test Action Group; an industry standard for verifying designs and testing printed circuit boards after manufacture - it specifies the use of a dedicated debug port implementing a serial communications interface for low-overhead access without requiring direct external access to the system address and data buses.